Xilinx launches data center accelerator for HPC


Xilinx introduced its latest data center accelerator, the Alveo U55C, which it says is its most powerful accelerator to date thanks to a change in memory.

For the most part, the FPGA-powered Alveo U55C is similar to its predecessor, the Alveo U280. But the U280 has 8GB of HBM2 memory and 16GB of DDR4 DRAM, while the U55C comes with 16GB of HBM2 memory and no DDR4. HBM2 is considerably faster and more expensive than DDR4 memory.

By upgrading to all HBM2 and removing DDR4, Xilinx is able to increase performance and significantly reduce power and size. The Alveo U55C is a single-slot, full-height, half-length (FHHL) form factor compared to the full-height, full-length, and double-width form of the U280. It also has a much lower power consumption, 150W versus 215W.

The smaller form factor offers greater compute density in the same space, suitable for creating dense clusters based on the Alveo accelerator. It is designed for high density streaming data, high I / O calculations, and scalable applications such as big data analytics and AI.

“We are changing Alveo’s position in the data center,” said Nathan Chang, HPC product manager at Xilinx, “and it’s not just for niche architectures or very specific data issues anymore. The goal is to create denser, scalable Alveo clusters to target HPC workloads. That’s why we designed this map.

The U55C supports RDMA integration over Converged Ethernet (RoCE) v2 and Message Passing Interface (MPI). HPC application developers can use the Xilinx Vitis software platform to build scalable applications that span multiple Alveo cards, regardless of server platforms and network infrastructure used.

Xilinx claims that RoCE v2, 200 Gbps bandwidth and Vitis API-driven clustering allow an Alveo network to compete with InfiniBand in performance and latency without network vendor lock-in. The Vitis platform and tools make hardware more accessible to software developers and data scientists without requiring hardware expertise. Vitis supports major AI frameworks such as Pytorch and Tensorflow, as well as high level programming languages ​​such as C, C ++, and Python.

As part of the briefing, Chang spoke about an HPC customer use case, the Australian national science agency, CSIRO, and the Square Kilometer Array (SKA) observatory of 131,000 radio antennas he is building. A group of 420 Alveo U55C cards processes the real-time signal of the data collected by the antennas, with an overall throughput of 15 TB.

By evolving on multiple Alveo U55C boards, performance with SKA tools has quintupled compared to x86 processors, while requiring half the number of servers and less than half the power compared to standard GPUs, according to Xilinx.

The Xilinx Alveo U55C is available on the company’s website or from authorized Xilinx distributors. It will also be available through public cloud-based FPGA-as-a-service providers for remote assessment, as well as selected colocation data centers for private overviews. General availability is not expected until the second quarter of next year.

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